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Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications

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3 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Shih-Lun Chen ; Chia-Sheng Tsai

A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltage-tolerant applications is proposed. The new proposed I/O buffer can receive input signals with a voltage swing twice as high as the normal power supply voltage (VDD). It has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005

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