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To reduce drastically the dynamic power (PAT) and the leakage power (PST), while increasing the operating speed of a CMOS square-root (SR) circuit, a new SR algorithm and a self-controllable-voltage-level (SVL) circuit, consisting of a single CMOS switch, have been developed. They can not only drastically decrease the number of gates (Gc) in the critical path and the total number of logic gates (G), but also considerably reduce the leakage power. Gc and G of the new 8-bit, 0.16-μm CMOS SR circuit are greatly reduced to 30 and 97, 50.0% and 51.3%, respectively, of those of a conventional SR circuit. Thus, the maximum operating frequency (fc) of the new SR circuit at a supply voltage (VDD) of 1.5 V is 581 MHz, 1.62 times faster than the 358 MHz of the conventional SR circuit. PAT of the new SR circuit, at fc of 200 MHz and VDD of 1.5 V, is reduced to 309 μW, 54.3% of the 569 μW of the conventional SR circuit. PST of the new SR circuit is only 8.8 nW, 1.36% of the 647 nW of the conventional SR circuit.