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A low-power high-SFDR CMOS direct digital frequency synthesizer

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3 Author(s)
Jinn-Shyan Wang ; Dept. of Electr. Eng., Chung-Cheng Univ., Chia-Yi, Taiwan ; Shiang-Jiun Lin ; Chingwei Yeh

A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters selection method, a reduced multiplier, a speeded-up adder/subtracter, an extra pipeline stage, and supply voltage scaling, are used to make the design more easily synthesizable and much more power efficient. A synthesized 0.35-μm DDFS, with an SFDR of -100 dBc, runs up to 100-MHz and consumes only 26.2-mW with a supply voltage of 1.7-V. The power efficiency is 0.26-mW/MHz, which represents an enhancement of more than 90% compared to the conventional DDFSs.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005