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In this paper, a scheme for power reduction based on cluster voltage scaling (CVS) for gate-level design of the VLSI circuits is presented. To increase the power reduction efficiency of the previous CVS techniques, a new low power level-shifter is utilized in the circuit. In addition, the concept of transistor ordering has been used to further reduce the power consumption. This technique shows an average improvement of 7% compared to the previous CVS circuits. The impact of CVS and its modified version on the reduction of short-circuit and leakage power are also discussed.