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In this paper, we propose a low-power SRAM design by reducing the accessed bit line capacitance. Each column is divided into divisions. Each division consists of equal number of cells connected together with a local bit line and one local sense amplifier. The divisions are connected together with a global bit line that is also connected to the write, precharge, and reading sense amplifier circuits. During write operation, the global bit lines is slightly discharged to develop a small voltage difference on the accessed local bit lines enough for the local sense amplifier to amplify it to full swing on the local bit lines pair only. The experimental results show reduction in the power consumption that can reach more than 88% with no performance degradation. The architecture is flexible to be used according to the power, and area budget.
Date of Conference: 23-26 May 2005