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An efficient VLSI architecture for the computation of the convolution-based discrete wavelet transform (DWT) is presented. The proposed architecture, employing two processing elements and a single buffer in a pipeline mode, enhances the processing time by appropriately decomposing the overall computations and distributing them equally between the two processing elements. The data flow, both within and between the processing elements, is streamlined, making use of the buffer and employing multiple input data paths within the processing elements. The parallelism of operations carried out by the computational blocks in each processing element is made more effective by equalizing the data paths used in these blocks. HSPICE and Verilog simulation results are presented to show that a circuit, whose design is based on the proposed architecture, is, in comparison with other existing architectures, fast and efficient for DWT computation, with a modest decrease in the area.
Date of Conference: 23-26 May 2005