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Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arrays. Such filters have high computational complexity and often require arithmetic throughputs of hundreds of millions of floating point operations per second, especially in the case of potential radio frequency beamforming applications. A novel high-throughput distributed parallel processor (DPP) architecture is proposed that is suitable for on-chip real-time VLSI/FPGA direct-form 3D IIR digital filter implementations. Using the proposed architecture and Matlab/Simulink and Xilinx simulation software, the design and bit-level simulation of a first-order highly-selective FPGA-based 3D IIR frequency-planar filter circuit is reported for 3D plane-wave filtering.