Referenced Items are not available for this document.
The proposed 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing amplifiers (summing nodes) connected to incoming data and feedback loops. Two parallel branches consisting of equalizing amplifier and two flip-flops each are also present and followed by a MUX. The design is verified by HSPICE using 0.18 μm CMOS process parameters. Simulation results show an increase of horizontal and vertical eye opening at data rates up to 8 Gbit/s. Data is transmitted over a 34" FR4 backplane with BER less than 10-15. The total power consumption is 12mW at a 1.8V supply.
Published in:
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Date of Conference: 23-26 May 2005
- Page(s):
- 1274 - 1277 Vol. 2
- Print ISBN:
- 0-7803-8834-8
- INSPEC Accession Number:
- 8581218
- Digital Object Identifier :
- 10.1109/ISCAS.2005.1464827
- Product Type:
- Conference Publications
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