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Pipelining technique for energy-aware datapaths

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5 Author(s)
Wei-Sheng Huang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tay-Jyi Lin ; Shih-Hao Ou ; Chih-Wei Liu
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This paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is free of race from the succeeding one, and when the glitch is minimal. Then, the clock pulses of the unused pipeline registers are gated to reduce the energy dissipation. Compared to the conventional clock gating approach, our proposed on-demand pipelining eliminates all redundant clock pulses whenever the peak datarate is not reached. Moreover, our method has a constant input-to-output latency for all operation modes, which significantly simplifies the integration tasks. In our simulations, the proposed on-demand pipelining saves up to 80% energy of conventional pipelined datapaths, and it can reduce about 34%∼39% energy dissipation of those with gated-clock only.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005