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Design and analysis of communication subsystems is a crucial issue for system-on-chip design, where uncertainty in communication by very deep sub micron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The methodology combines both BA space exploration as well as generation analysis of arbitration policies to guarantee a feasible solution at transaction level where optimized policy is assigned. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. Heuristic arbitration policies as well as Markov decision process (MDP) based policies have been simulated over a queueing model of the architecture and compared with respect to performance metrics like queue length, time spent in buffer and power consumption. The paper presents BA synthesis results for a network processor.