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The design in a standard 0.13 μm CMOS technology of a 1.2 V baseband block (DAC+filter), intended for wireless applications (UMTS, WLANs), is presented. A transimpedance stage is placed between the two functional blocks to improve the static and dynamic linearity performance of the current steering DAC with respect to a solution in which the DAC outputs are directly connected to the following reconstruction filter. Transistor level simulations have been used to evaluate the DAC DNL-INL and the dynamic linearity performance (OIP3) at the filter output. A comparison with the simulated performance of an implemented block which does not use the DAC output transimpedance stage confirms the effectiveness of the proposed solution.