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A low power scheduling method using dual Vdd and dual Vth

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4 Author(s)
Kun-Lin Tsai ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Szu-Wei Chang ; Feipei Lai ; Shanq-Jang Ruan

As technology scales down to nanometer dimensions, static power consumption has become more and more important. We propose a low power method to manage power consumption; it considers dual supply voltage (Vdd) and dual threshold voltage (Vth) at the same time to deal with the scheduling problem in the behavioral synthesis stage. A flexible design space of power, and a better performance can be achieved when we use the proposed method. An algorithm combining GA (genetic algorithm) and SA (simulated annealing) is used to solve the scheduling problem. Experimental results illustrate 41.6% power reduction on average.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005