By Topic

A new design method to modulo 2n-1 squaring

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bin Cao ; Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore ; Srikanthan, T. ; Chip-Hong Chang

The paper presents a novel method for modulo 2n-1 squaring using the exponent reduction property of powers of 2 modulo 2n-1. An exponent triangle is created to simplify the design approach. In contrast to methods based on the periodic properties of powers of 2 modulo 2n-1, our graph based design method is appealing and yields a solution with direct correspondence to the modulo squaring structure. Simulation results show that the carry saver adder (CSA) tree for the proposed method lowers the hardware cost by more than half of that generated by the multiplier-based method. The overall delay has also been reduced by two levels of the CSA tree in general.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005