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A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis

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2 Author(s)
Nakamura, Y. ; Media & Inf. Res. Labs., NEC Corp., Kawasaki, Japan ; Yoshimura, T.

The paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in which chip-scale gate-level circuits, including processors and memory, are affected by gated-clock power reduction and the voltage drop due to electrical resistance (IR-drop). Chip-scale power estimation based on simulation patterns generally takes a long time. To obtain accurate estimation results based on simulation patterns in a short time, we introduce three approaches: (1) hierarchical circuit and simulation pattern partitioning; (2) memory modeling; (3) processor modeling. First, the target LSI design, after placing and routing, is partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity. The experimental results for a commercial 0.18 μm-technology digital TV chip show that our proposed method can get almost the same results obtained by the conventional method without partitioning and can do it 25 times faster.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005

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