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A high performance architecture of EBCOT encoder in JPEG 2000

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4 Author(s)
Yan Xiaolang ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Qin Ying ; Yang Ye ; Ge Haitong

A high performance architecture for EBCOT in JPEG 2000 is proposed. The architecture consists of a column-and-pass dual parallel context modeling unit capable of the simultaneous processing of four samples, and a pipelined binary arithmetic coder based on a two-context window running at double the clock frequency to match the processing rate of the context modeling unit. Simulation results show that this design reduces processing time by about 60% compared with existing pass-parallel architectures and is able to process a 512×512 grayscale image in approximately 4 ms at 100 MHz system clock rate.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005