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Design space exploration on heterogeneous network-on-chip

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4 Author(s)
R. S. Cardoso ; GME-Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil ; M. E. Kreutz ; L. Carro ; A. A. Susin

High performance SoC designs using networks-on-chip (NoCs) take benefit from the speed-up coming from the available parallelism. However, the spatial parallelism causes an impact on the resulting area of the SoC. In this paper, a heterogeneous NoC is considered, as an alternative to reduce the total area overhead caused by the routers on a NoC architecture. By employing an optimized mix of routers with different requirements in terms of area, a network comprising a trade-off between latency and area is achieved. We use an optimization algorithm that automatically finds a network architecture that complies with the performance constraints, keeping the area cost as small as possible. We demonstrate the effectiveness of our approach by mapping the communications of two applications on an optimized heterogeneous NoC architecture, and show area savings of 35%, while maintaining performance.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005