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A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders

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2 Author(s)
S. Bates ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada ; G. Block

Low-density parity-check convolutional codes complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice and video and packet switching networks. In this paper we introduce these codes and propose a memory-based decoder architecture that is well suited for implementation on field-programmable gate arrays. We present an overview of the architecture and demonstrate its efficiency over register-based architectures. We then discuss a realization of this architecture that can trade performance for throughput and can achieve up to 120 Mb/s of information throughput and a BER as low as 2 × 10-6 at an Eb/Nq of 3 dB on an Altera Stratix FPGA. For a first-generation implementation this compares favorable with current block-oriented decoder implementations.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005