By Topic

High level hardware/software communication estimation in shared memory architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
S. Pandey ; Inst. of Microelectron. Syst., Darmstadt, Germany ; H. Zimmer ; M. Glesner ; M. Muhlhauser

The paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of an SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters, we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by a Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for different bus widths. From the estimated figures, we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.

Published in:

2005 IEEE International Symposium on Circuits and Systems

Date of Conference:

23-26 May 2005