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Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder

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3 Author(s)
Hatakawa, Y. ; Graduate Sch. of Eng., Hokkaido Univ., Sapporo, Japan ; Yoshizawa, S. ; Miyanaga, Y.

The paper presents a robust VLSI architecture which avoids most of the malfunctions and makes the system work correctly. The proposed architecture realizes robustness only by using small switches. The switches avoid broken computing modules and reconfigure data flows between the normal modules. This architecture has advantages compared to conventional duplicated systems in terms of resource utilization and circuit area, and improves yield rate. We designed a Viterbi decoder based on the proposed robust architecture and evaluated its effectiveness in CMOS technology.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005