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Device technology for body biasing scheme

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8 Author(s)
Imai, K. ; Adv. Device Dev. Div., NEC Electron. Corp., Kanagawa, Japan ; Yamagata, Y. ; Masuoka, S. ; Kimuzuka, N.
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We report power-aware 65-nm node CMOS device technology suitable for a body biasing scheme. For high-performance CMOS, both channel and halo profiles have been optimized to enhance the body-bias effect of 45-nm gate length devices. Standby leakage reduction without device reliability compromise has been demonstrated with simultaneous voltage control of the body bias and power supply. Moreover, high-k gate dielectric "HfSiON" has been adopted to reduce both gate leakage and GIDL, which are the dominant standby leakage components of low standby power CMOS.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005