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We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.