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Low density parity check (LDPC) codes have shown 3 to 5 dB coding gain, at bit error rates (BER) around 10-5, over the uncoded partial response maximum-likelihood (PRML) channels. However, the error floor of LDPC codes is still an open question and is one of the major concerns in applying LDPC codes in high density receding channel. Due to the suboptimal nature of decoding schemes and the difficulties in code spectrum analysis, the performance analysis of LDPC code at very low BER region is very difficult, if not impossible. Therefore, the performance of LDPC codes is usually evaluated through Monte Carlo simulations. The sequential nature of the conventional C simulations limits their capability for BER investigation. It takes months to evaluate the performance of codes in partial response (PR) channel at 10-9 BER using optimized C code and a 2 GHz computer. To investigate the error floors, a high-throughput, fully-reconfigurable field programmable gate array (FPGA) platform was developed for the evaluation of LDPC codes in PR channel. In this paper, the architecture, main features and throughput of the channel simulator on FPGA was described. The error floor of one type of LDPC code is shown as an example.