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High performance and low complexity Max-Log-MAP algorithm for FPGA turbo decoder

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2 Author(s)
Mao-Hsiu Hsu ; Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei ; Jhin-Fang Huang

In this paper, we focus on implementing turbo decoder compliant with 3GPP spec, we adopted sliding window method with forward state metric as an accuracy initialization value and a modified Max-Log-MAP algorithm which modify extrinsic information by a scaling factor R. Then, we can implement the whole turbo decoder with a single-decoder structure, producing high data throughput with lower logic gates usage. The FPGA design of our proposed structure (SW-modified Max-Log-MAP) results in only 0.1 dB away from the optimal structure (SW-Log-MAP) at BER=10-4. It also saves about 29% hardware cost than the optimal structure

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The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005.  (Volume:2 )

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