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Utilizing an integrated yield management system to improve the return on investment in IC manufacturing

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3 Author(s)
Castrucci, P. ; Paul Castrucci & Associates Inc., Boston, MA, USA ; Dickerson, G. ; Bakker, D.

The authors describe how a yield management system (YMS) could be designed to provide tools to quickly find and fix process and equipment defect problems in 16 Mbit DRAM IC manufacturing. The proposed system design consists of the KLA 2110 wafer inspection system (with sensitivity down to 0.25 μm for 16 Mbit DRAM manufacturing), optical and SEM (scanning electron microscope) defect review stations, wafer prober stations, reticle inspectors, a dielectric failure detection system, a defect image storage unit, an analysis workstation, and a host computer where work-in-process and yield information is stored

Published in:

Semiconductor Manufacturing Science Symposium, 1991. ISMSS 1991., IEEE/SEMI International

Date of Conference:

20-22 May 1991