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An integrated reset / pulse pile-up rejection circuit for pixel readout ASIC's

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11 Author(s)
P. Bastia ; Alenia Spazio S.p.A., Vimodrone, Italy ; G. Bertuccio ; F. Borghetti ; S. Caccia
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We present a compact and low power integrated circuit designed to control the reset and performs the pulse pile-up rejection in multi-channel spectroscopic-grade ASIC's. The circuit has been implemented in 0.35 mum CMOS technology with an area of 60times80 mum2 and null static power consumption. These features makes this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X and gamma ray pixel detectors.

Published in:

Nuclear Science Symposium Conference Record, 2004 IEEE  (Volume:3 )

Date of Conference:

16-22 Oct. 2004