Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit

A 10 Gb/s clock and data recovery (CDR) circuits which extract the clock signal from non-return-zero (NRZ) random data stream are very important to the 10-gigabit -per-second integrated receivers. The half-rate linear phase detector for 10-Gb/s clock and data recovery (CDR) circuit is designed to 0.18-um standard CMOS technology. This half-rate phase detector is composed of four latches and two exclusive OR (XOR) gates. The proposed circuits of phase detector provide a linear characteristic and it has a configuration of MOS current-mode logic (MCML) gates