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Load-balanced combined input-crosspoint buffered packet switch and long round-trip times

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3 Author(s)
R. Rojas-Cessa ; Dept. of Comput. & Electr. Eng., New Jersey Inst. of Technol., Newark, NJ, USA ; Z. Dong ; Z. Guo

The amount of memory in buffered crossbars is proportional to the number of crosspoints, or O(N2), where N is the number of ports, and to the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under high-speed data flows. A long distance between these two components can make a buffered crossbar costly to implement. In this letter, we propose a load-balanced combined input-crosspoint buffered packet switch that uses small crosspoint buffers and no speedup. The proposed switch reduces the required size of the crosspoint buffers by a factor of N and keeps the cells in sequence.

Published in:

IEEE Communications Letters  (Volume:9 ,  Issue: 7 )