By Topic

Performance modeling of resonant tunneling-based random-access memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hui Zhang ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; Mazumder, P. ; Li Ding ; Kyounghoon Yang

Resonant tunneling-based random-access memories (TRAMs) have recently garnered a great amount of interest among memory designers due to their intrinsic merits such as reduced power consumption by elimination of refreshing operation, faster read and write cycles, and improved reliability in comparison to conventional silicon dynamic random access memories (DRAMs). In order to understand the precise principle of operation of TRAM memories, an in-depth circuit analysis has been attempted in this paper and analytical models for memory cycle time, soft error rate, and power consumption have been derived. The analytical results are then validated by simulation experiments performed with HSPICE. These results are then compared with conventional DRAMs to establish the claim of superiority of TRAM performance to DRAM performance.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:4 ,  Issue: 4 )