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A system for automated built-in self-test of embedded memory cores in system-on-chip

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2 Author(s)
Garimella, S. ; Dept. of Electr. & Comput. Eng.,, Auburn Univ., AL, USA ; Stroud, C.

A system for automatic generation of built-in self-test (BIST) for embedded memory cores in a system-on-chip (SoC) is presented. The BIST approach tests RAMs of any address and data bus widths and can test both single-port and dual-port RAMs operating in synchronous or asynchronous mode. A field programmable gate array (FPGA) independent BIST model is developed using VHDL. The parameterized VHDL model has been synthesized and used to test various sizes and types of embedded RAMs in SoCs and FPGAs.

Published in:

System Theory, 2005. SSST '05. Proceedings of the Thirty-Seventh Southeastern Symposium on

Date of Conference:

20-22 March 2005