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The work presents an efficient architecture more easily realized with FPGA for fine multi-rate symbol timing recovery in software radio QPSK demodulation. This all-digital timing tracking loop is a second order non-data aided feedback loop containing a Gardner timing error detector. It has a power efficient cascaded structure consisting of parallel cascaded integrator-comb (CIC) filters followed by a linear interpolator and can perform arbitrary sample rate conversion and fine timing correction. By jointly optimizing the two building blocks, the bit error rate is noticeably reduced and computational complexity is drastically decreased. Thus, implementing software radio QPSK demodulation with FPGA becomes easier. An analysis of a QPSK demodulation timing recovery simulation is presented.