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Design and optimization of a hot-carrier resistant high-voltage nMOS transistor

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3 Author(s)
M. Annese ; TPA Groups, STMicroelectronics, Milano, Italy ; S. Carniello ; S. Manzini

The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed.

Published in:

IEEE Transactions on Electron Devices  (Volume:52 ,  Issue: 7 )