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This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental fT/fmax of the high-speed device are 17/28 GHz, the second fastest reported fT for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured fT/fmax of 12/30 GHz and BVCEO of over 25 V produces a Johnsons product well above 300 GHz ·V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.
Date of Publication: July 2005