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VLSI implementation of MIMO detection using the sphere decoding algorithm

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6 Author(s)
Burg, A. ; Swiss Fed. Inst. of Technol., Zurich, Switzerland ; Borgmann, M. ; Wenk, M. ; Zellweger, M.
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Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the ℓ-instead of ℓ2-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 7 )

Date of Publication:

July 2005

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