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Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

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8 Author(s)
von Arnim, K. ; Infineon Technol., Corporate Res., Munich, Germany ; Borinski, E. ; Seegebrecht, P. ; Fiedler, H.
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The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.

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Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 7 )