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A 19-mW 2.6-mm2 L1/L2 dual-band CMOS GPS receiver

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4 Author(s)
Jinho Ko ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Jongmoon Kim ; Sanghyun Cho ; Kwyro Lee

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-μm CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm2 die area including the ESD I/O pads.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 7 )

Date of Publication:

July 2005

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