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Dual high-κ gate dielectric with poly gate electrode: HfSiON on nMOS and Al2O3 capping layer on pMOS

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2 Author(s)
Li, Hong-Jyh ; Int. SEMATECH, Austin, TX, USA ; Gardner, M.I.

In this letter, a novel dual high-κ approach, different high-κ dielectrics in nMOS and pMOS, with poly Si gate electrode is introduced. By turning the Fermi-pinning effect into an advantage, this dual high-κ approach achieved a lower Vtp and a symmetrical Vtn/Vtp over a wide range of channel lengths for potential high-κ/poly Si CMOS application. In addition to the Vt control, this approach also can improve the drive current ratio between nMOS and pMOS, which would further scale the CMOS area by reducing the pMOS width.

Published in:

Electron Device Letters, IEEE  (Volume:26 ,  Issue: 7 )

Date of Publication:

July 2005

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