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Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

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3 Author(s)
Chao-Tsung Huang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Po-Chih Tseng ; Liang-Gee Chen

In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive pyramid algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.

Published in:

IEEE Transactions on Circuits and Systems for Video Technology  (Volume:15 ,  Issue: 7 )