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Nine-coded compression technique for testing embedded cores in SoCs

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3 Author(s)
Tehranipoor, M. ; Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland Baltimore County, MD, USA ; Nourani, M. ; Chakrabarty, K.

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 6 )

Date of Publication:

June 2005

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