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A silicon compiler for digital signal processing: Methodology, implementation, and applications

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4 Author(s)
Yassa, F.F. ; General Electric Corporate Research and Development Center, Schenectady, NY ; Jasica, J.R. ; Hartley, R.I. ; Noujaim, S.E.

This paper describes a fully integrated silicon compilation tool geared towards digital signal processing applications. The silicon compiler presented here uses a bit-serial architecture with a 1.25- µm CMOS cell library. It accepts as its input a high-level description language tailored for digital signal processing algorithms. The language supports the basic signal processing constructs such as multiplication, addition, subtraction, sample delays, logical operators, relational operators, as well as a conditional assignment. The compiler is equipped with behavioral, logic, and fault simulators, and performs placement and routing. The paper also details the use of the silicon compiler for the implementation of classical DSP algorithms: digital filters, FFT, programmable filters, as well as other more specialized applications such as adaptive algorithms and waveform synthesis. Moreover, some techniques are presented to implement more complex mathematical functions commonly used in DSP. The results of chip designs using the compiler and its impact on future designs are highlighted.

Published in:

Proceedings of the IEEE  (Volume:75 ,  Issue: 9 )

Date of Publication:

Sept. 1987

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