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ASIC design methodologies are assessed from the system designer's point of view by comparing the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard devices. ASIC methodologies include programmable logic devices, gate arrays, standard cells, and full custom, all primarily in 2-µm CMOS, at production volumes of 1 to 100K units per year and at complexities of 5OO to 20 000 gates per device. It is shown that "gates per pin" is the key determinant of total IC-related cost. Products containing ASIC cost less than those containing SSI/MSI, since ASICs raise the number of gates per pin from 2 to a range of 40-200. More surprising, products using ASIC devices cost less than products containing combinations of standard LSI/VLSI and SSI/MSI, if their gates per pin is 2-3 times that of the products containing standard devices. Each design methodology has regions, or market segments, where it is competitive. But there are large regions of small cost differences between two ASIC methodologies. Currently, these regions use primarily the older methodologies, i.e., gate arrays at low production volumes and full custom at high volumes. They also provide future opportunities for standard cells. Currently, IC manufacturing cost accounts for about 15 percent of the logic-related total cost, field maintenance for 17 percent, device and system development for 11 percent, and systems related manufacturing cost for 57 percent. These percentages are expected to migrate to 17, 20, 13, and 50 percent, respectively, by 1990. Our ASIC techno-economic assessment is summarized in 27 nomograms, figures, and charts.