By Topic

Circuit analysis, logic simulation, and design verification for VLSI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ruehli, Albert E. ; IBM Thomas J. Watson Research Center, Yorktown Heights, NY ; Ditlow, Gary S.

In this paper, we consider computer-aided design techniques for VLSI. Specifically, the areas of circuit analysis, logic simulation and design verification are discussed with an emphasis on time domain techniques. Recently, researchers have concentrated on two general problem areas. One important problem discussed is the efficient, exact-time analysis of large-scale circuits. The other area is the unification of these techniques with logic simulation and design verification technique in so called multimode or multilevel systems.

Published in:

Proceedings of the IEEE  (Volume:71 ,  Issue: 1 )