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After a discussion of the main problems encountered in conventional methods used for testing high-speed LSI/VLSI logic, a new approach, to be called the "in-situ testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability-that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.