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A prototype for a fault tolerant parallel signal processor

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3 Author(s)
B. R. Musicus ; Res. Lab. of Electron., MIT, Cambridge, MA, USA ; A. Aliphas ; A. J. Wei

The authors describe a hardware prototype of a fault-tolerant parallel digital signal processor (DSP) that uses the single fault correction scheme of B.E. Musicus and W. S. Song (1987, 1990). Ten of the sixteen DSP-32 C processors perform identical linear operations on ten different data streams (a complex fast Fourier transform (FFT) for a sonar beamforming application), three do arithmetic checksums on the input data and FFTs on these checksums and one generates the syndromes and does fault detection and correction using a generalized likelihood ratio test (GLRT). A faulty output from one of the first 13 processors can be detected and corrected without having to recalculate that output. The prototype is not itself fault-tolerant, but is intended to benchmark applications and to quantify the actual overheads involved in executing the fault-tolerance algorithm

Published in:

Application Specific Array Processors, 1990. Proceedings of the International Conference on

Date of Conference:

5-7 Sep 1990