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An integrable MOS neuristor line

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2 Author(s)
Kulkarni-Kohli, C. ; University of Maryland, College Park, MD ; Newcomb, R.W.

An integrable MOS design of a neuristor line simulating the conventional properties is presented, the line requiring as few as two sections to simulate the desired properties. In addition the line is low power while consuming no power during the resting state.

Published in:

Proceedings of the IEEE  (Volume:64 ,  Issue: 11 )