By Topic

Algorithmic mapping of neural network models onto parallel SIMD machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kumar, V.K.P. ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Przytula, K.W.

The authors consider parallel implementation of neural network computations of fine grain SIMD machines. The authors show a mapping of a neural network having n nodes and e connections onto a parallel machine having (n+e) PEs arranged in an array of √n+e×√n+e PEs such that routing for each update iteration of the recall phase can be performed in 24(√n+e-1) elemental data shifts. The array uses simple PEs and few local registers to perform the routing and computations. The method is simple and is well suited for implementation of various classes of neural networks on many currently available parallel machines

Published in:

Application Specific Array Processors, 1990. Proceedings of the International Conference on

Date of Conference:

5-7 Sep 1990