By Topic

A 3-D wafer scale architecture for early vision processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
S. T. Toborg ; Hughes Res. Lab., Malibu, CA, USA

A massively parallel SIMD cellular computer is designed for processing early vision algorithms based on regularization theory and Markov random field (MRF) models. Algorithmic requirements and implementation issues are reviewed in detail for edge detection/surface reconstruction. The development of 3-D wafer scale integration (WSI) technologies that offer an ideal medium for implementing many early vision algorithms is discussed. An edge detection algorithm is mapped to the 3-D WSI computer that consists of a 128×128 array of processors formed by stacking 15 four inch CMOS wafers. This mapping is used as the basis for an enhanced array processor tailored for multiresolution MRF processing. Enhancements are proposed that would boost peak performance to over a trillion operations per second, using a stack of 40 wafers, with a total system volume of 820 cm3 and consuming about 370 W

Published in:

Application Specific Array Processors, 1990. Proceedings of the International Conference on

Date of Conference:

5-7 Sep 1990