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On sign bit assignment for a vector multiplier

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1 Author(s)
Kai-Ping Yiu ; Lockheed Palo Alto Research Laboratory, Palo Alto, CA

A simple sign bit assignment scheme for each SHIFT operation of a vector multiplier is presented. This new scheme is capable of determining the correct sign for a shifted sum independent of overflow conditions during each ADD operation.

Published in:

Proceedings of the IEEE  (Volume:64 ,  Issue: 3 )

Date of Publication:

March 1976

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