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Design of FPGA hardware for a real-time blind source separation of fetal ECG signals

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4 Author(s)
C. Chareonsak ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; Farook Sana ; Yu Wei ; Xiong Bing

A common problem when monitoring fetal ECG (FECG) signal is the interference by maternal ECG (MECG). The fetal heart is very small and thus the electrical current it generates is much lower than that of the mother. In order to extract the fetal ECG for proper clinical diagnostic, some adaptive filtering technique can be used to remove or suppress the maternal ECG. Often, a number of electrodes are placed around the general area of the fetus to pick up multiple FECG signals. In this case, blind source separation (BSS) algorithm can be used to separate the FECG from the MECG effectively. Blind source separation of independent sources from their mixtures is a common problem in many real world multi-sensor applications. However, the algorithm requires high computation and thus a real-time implementation using software is not practical, or expensive. In this paper, we propose and implement an efficient and low-cost FPGA (field programmable gate array) hardware architecture for the realization of a real-time BSS in the application of FECG signal separation. The FPGA design implements the modified Torkkola's BSS algorithm for audio signals based on ICA (independent component analysis) technique.

Published in:

Biomedical Circuits and Systems, 2004 IEEE International Workshop on

Date of Conference:

1-3 Dec. 2004