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The carry-completion sensing adders (CCSAs) are widely adopted for fast average-case low energy asynchronous (async) adders. Despite its carry-completion sensing property, completion detection in the conventional CCSAs suffers from potential timing violations (PTVs); conventional CCSAs would otherwise require additional hardware or detailed design iterations. In this paper, we describe a robust low voltage (1.1 V) medium-speed low energy (average of 4.8 ns and 317 fJ in a 035 μm CMOS process) async 2-bit CCSA for power-critical biomedical instruments such as hearing instruments. In our design, the generation of the sum signals is always faster than that of the carry-out signals, thereby eliminating any PTVs. When compared to the two 1-bit CCSAs of equal robustness, our design is 16% faster and requires 5% less energy.