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This paper presents a new chip-structure to implement FFT. The key features of this structure are parallel computation and hierarchical memory partition. This new structure is aimed at both increasing the data bandwidth and decreasing the power dissipation, and it has been implemented on a 0.15-μ manufacture process FPGA (field programmable gate array) chip. At a core supply voltage of 1.5 V and a working clock of 50 MHz, this chip can complete 1024-point 16-bit complex FFT in a little more than 30 μs while the chip core consumes about 500 mW power.